With the continuous development and improvement of semiconductor technology, the critical dimensions of features in monolithically integrated semiconductor devices tend to shrink. As a result of this tendency, problems emerge for nanometer regime transistor structures. For example, a tri-gate “Fin” type transistor is shown in FIG. 1 (not necessarily a FinFET—can be a junction FET instead). Here it will also be referred to as a 3D transistor. Contrary to the planar channel structure in a conventional 2D transistor, the latter is replaced by a super-thin 3D silicon fin which rises vertically from a silicon substrate. Control of conduction may be had around at least three sides of the channel rather than just one as was the case for conventional planar channel structures.
In the 3D transistors, the silicon fins are vertical so that even wide channel transistors may be placed more closely to each other. Thus a greatly increased packing density for transistors is made possible. Furthermore, and as alluded to above, in the 3D transistor, conduction control for the channel may be realized by mounting a respective one or more gate electrodes about each of the three raised faces (i.e. two sides and a top face of the fin), which is different from a 2D transistor wherein a gate is disposed only adjacent to the top face of the 2D channel structure. Such design of the 3D transistor allows more current to flow when the transistor is controlled via the gate to be in the “ON” state, and the current is reduced to approximately zero when the transistor is controlled via the gate to be in the “OFF” state. The 3D transistors can very quickly switch between the two states, thereby obtaining higher performance and efficiency.
An embedded SiGe process has been widely used in the manufacturing procedure of MOS transistors to increase the charge carrier mobility of the MOS transistors, both in the 2D transistors and 3D transistors.
However, with the miniaturization of CD (critical dimension), in the manufacturing procedure of the 3D transistors, as shown in FIG. 2, the deposited SiGe material around the adjacent fins in MOS transistors can be readily bridged with that of adjacent fins, so that the performance of the 3D transistors is deteriorated (for example due to shorting or capacitive cross-coupling between immediately adjacent SiGe layers).
It is to be understood that this background of the technology section is intended to provide useful background for understanding the here disclosed technology and as such, the technology background section may include ideas, concepts or recognitions that were not part of what was known or appreciated by those skilled in the pertinent art prior to corresponding invention dates of subject matter disclosed herein.